PATH:
opt
/
cloudlinux
/
venv
/
lib
/
python3.11
/
site-packages
/
numpy
/
distutils
/
checks
#if defined(DETECT_FEATURES) && defined(__INTEL_COMPILER) /* * Unlike GCC and CLANG, Intel Compiler exposes all supported intrinsics, * whether or not the build options for those features are specified. * Therefore, we must test #definitions of CPU features when option native/host * is enabled via `--cpu-baseline` or through env var `CFLAGS` otherwise * the test will be broken and leads to enable all possible features. */ #ifndef __F16C__ #error "HOST/ARCH doesn't support F16C" #endif #endif #include <emmintrin.h> #include <immintrin.h> int main(int argc, char **argv) { __m128 a = _mm_cvtph_ps(_mm_loadu_si128((const __m128i*)argv[argc-1])); __m256 a8 = _mm256_cvtph_ps(_mm_loadu_si128((const __m128i*)argv[argc-2])); return (int)(_mm_cvtss_f32(a) + _mm_cvtss_f32(_mm256_castps256_ps128(a8))); }
[-] cpu_asimdfhm.c
[open]
[-] cpu_f16c.c
[open]
[-] cpu_neon.c
[open]
[+]
..
[-] extra_vsx_asm.c
[open]
[-] cpu_sse41.c
[open]
[-] cpu_avx2.c
[open]
[-] cpu_avx512_knl.c
[open]
[-] cpu_fma4.c
[open]
[-] extra_avx512bw_mask.c
[open]
[-] extra_vsx4_mma.c
[open]
[-] cpu_vxe.c
[open]
[-] cpu_sse2.c
[open]
[-] cpu_avx512_knm.c
[open]
[-] cpu_avx512_skx.c
[open]
[-] cpu_neon_fp16.c
[open]
[-] cpu_vsx4.c
[open]
[-] cpu_neon_vfpv4.c
[open]
[-] cpu_sse42.c
[open]
[-] cpu_avx512_spr.c
[open]
[-] cpu_asimd.c
[open]
[-] cpu_fma3.c
[open]
[-] cpu_asimdhp.c
[open]
[-] cpu_vx.c
[open]
[-] cpu_vsx3.c
[open]
[-] cpu_avx512_cnl.c
[open]
[-] cpu_avx.c
[open]
[-] test_flags.c
[open]
[-] cpu_popcnt.c
[open]
[-] cpu_vxe2.c
[open]
[-] cpu_ssse3.c
[open]
[-] cpu_vsx.c
[open]
[-] cpu_sse.c
[open]
[-] cpu_asimddp.c
[open]
[-] cpu_sse3.c
[open]
[-] extra_avx512f_reduce.c
[open]
[-] cpu_avx512_clx.c
[open]
[-] cpu_avx512cd.c
[open]
[-] extra_avx512dq_mask.c
[open]
[-] cpu_avx512_icl.c
[open]
[-] cpu_xop.c
[open]
[-] cpu_avx512f.c
[open]
[-] cpu_vsx2.c
[open]