PATH:
opt
/
cloudlinux
/
venv
/
lib
/
python3.11
/
site-packages
/
numpy
/
distutils
/
checks
/** * Testing ASM VSX register number fixer '%x<n>' * * old versions of CLANG doesn't support %x<n> in the inline asm template * which fixes register number when using any of the register constraints wa, wd, wf. * * xref: * - https://bugs.llvm.org/show_bug.cgi?id=31837 * - https://gcc.gnu.org/onlinedocs/gcc/Machine-Constraints.html */ #ifndef __VSX__ #error "VSX is not supported" #endif #include <altivec.h> #if (defined(__GNUC__) && !defined(vec_xl)) || (defined(__clang__) && !defined(__IBMC__)) #define vsx_ld vec_vsx_ld #define vsx_st vec_vsx_st #else #define vsx_ld vec_xl #define vsx_st vec_xst #endif int main(void) { float z4[] = {0, 0, 0, 0}; signed int zout[] = {0, 0, 0, 0}; __vector float vz4 = vsx_ld(0, z4); __vector signed int asm_ret = vsx_ld(0, zout); __asm__ ("xvcvspsxws %x0,%x1" : "=wa" (vz4) : "wa" (asm_ret)); vsx_st(asm_ret, 0, zout); return zout[0]; }
[-] cpu_asimdfhm.c
[open]
[-] cpu_f16c.c
[open]
[-] cpu_neon.c
[open]
[+]
..
[-] extra_vsx_asm.c
[open]
[-] cpu_sse41.c
[open]
[-] cpu_avx2.c
[open]
[-] cpu_avx512_knl.c
[open]
[-] cpu_fma4.c
[open]
[-] extra_avx512bw_mask.c
[open]
[-] extra_vsx4_mma.c
[open]
[-] cpu_vxe.c
[open]
[-] cpu_sse2.c
[open]
[-] cpu_avx512_knm.c
[open]
[-] cpu_avx512_skx.c
[open]
[-] cpu_neon_fp16.c
[open]
[-] cpu_vsx4.c
[open]
[-] cpu_neon_vfpv4.c
[open]
[-] cpu_sse42.c
[open]
[-] cpu_avx512_spr.c
[open]
[-] cpu_asimd.c
[open]
[-] cpu_fma3.c
[open]
[-] cpu_asimdhp.c
[open]
[-] cpu_vx.c
[open]
[-] cpu_vsx3.c
[open]
[-] cpu_avx512_cnl.c
[open]
[-] cpu_avx.c
[open]
[-] test_flags.c
[open]
[-] cpu_popcnt.c
[open]
[-] cpu_vxe2.c
[open]
[-] cpu_ssse3.c
[open]
[-] cpu_vsx.c
[open]
[-] cpu_sse.c
[open]
[-] cpu_asimddp.c
[open]
[-] cpu_sse3.c
[open]
[-] extra_avx512f_reduce.c
[open]
[-] cpu_avx512_clx.c
[open]
[-] cpu_avx512cd.c
[open]
[-] extra_avx512dq_mask.c
[open]
[-] cpu_avx512_icl.c
[open]
[-] cpu_xop.c
[open]
[-] cpu_avx512f.c
[open]
[-] cpu_vsx2.c
[open]